1. Field of the Invention
The present invention relates to noise control in a semiconductor memory device.
2. Description of the Related Art
A typical semiconductor memory device such as the dynamic random access memory (DRAM) shown in FIG. 1 comprises a column address buffer 11 for storing a column address and a row address buffer 12 for storing a row address included in an address signal ADR. The row address buffer 12 is connected to a row decoder 13 that decodes the row address and supplies the decoded address to a word line driver 14, which drives corresponding word lines of a memory cell array 15 according to the decoded address data.
The column address buffer 11 is connected to a column decoder 16, which outputs decoded column address signals to a set of sense amplifiers 17. In a read operation, the sense amplifiers 17 amplify data read from the memory cell array 15 onto bit lines and output amplified data from the addressed column to an input-output (I/O) selector 18. In a write operation, the sense amplifiers 17 write data received from the input-output selector 18 into the memory cell array 15 at the addressed column. The input-output selector 18 is connected to an input buffer 19 and an output buffer 20 for external input and output of data DQ.
The DRAM comprises a timing generator circuit 21 for generating timing signals according to a row address strobe (RAS) signal and a column address strobe (CAS) signal, a refresh control circuit 22 for controlling refreshing of the memory cell array 15, an internal address counter 23, a first-stage circuit 30 for generating a write control signal (WE0) according to an initialize signal (INI) and a write enable signal (/WE), and an input-output control circuit 24 for generating an internal enable signal (RMB) according to the RAS and CAS signals, an output enable signal (OE), and the write control signal WE0 received from the first-stage circuit 30, and supplying the generated internal enable signal RMB to the input buffer 19 and output buffer 20.
During initialization, when the initialize signal INI is high, the first-stage circuit 30 drives the write control signal WE0 low, disabling write operations. During normal operations, when the initialize signal INI is low, the first-stage circuit 30 inverts the write enable signal /WE and passes the inverted signal as the write control signal WE0 to the input-output control circuit 24.
In a normal read operation, the RAS signal, CAS signal, and output enable signal OE are active (low), and the write enable signal /WE is inactive (high). The first-stage circuit 30 inverts the write enable signal /WE, driving the write control signal WE0 supplied to the input-output control circuit 24 low. As a result, the input-output control circuit 24 outputs an internal enable signal RMB enabling the output buffer 20. This allows data to be read from the memory region of the memory cell array 15 designated by the address signal ADR, and to be supplied to an external circuit through the sense amplifiers 17, the input-output selector 18, and the output buffer 20 as data DQ. When it begins supplying data DQ to the external circuit, the output buffer 20 outputs a commencement signal (not shown).
In a normal write operation, the RAS signal, CAS signal, and write enable signal /WE are active (low), and the output enable signal OE is inactive (high). The first-stage circuit 30 inverts the write enable signal /WE, driving the write control signal WE0 supplied to the input-output control circuit 24 high. As a result, the input-output control circuit 24 outputs an internal enable signal RMB enabling the input buffer 19. This allows data DQ received from the external circuit to be stored in a memory region of the memory cell array 15 designated by the address signal ADR.
During the read operation, the write enable signal /WE remains high, the inverted write control signal WE0 generated by the first-stage circuit 30 remains low, and the input-output control circuit 24 holds write operations disabled. As increasingly large-capacity semiconductor memory devices such as DRAMs have increasingly fine circuit lines, however, the large flow of current that occurs when the output buffer 20 outputs data DQ can cause considerable ground-bounce noise in the fine-line power wiring pattern. If the external write enable signal /WE is routed on a path substantially adjacent to the output buffer 20, the write enable signal /WE may be contaminated by noise, and the input-output control circuit 24 may misinterpret the logic level of the write control signal WE0. If the low level of the write control signal WE0 is misinterpreted as the high level, the input-output control circuit 24 will enable the input buffer 19, causing unintended writing of data in the memory cell array 15.
Japanese Patent Application Publication No. 06-21792 discloses a selector device with provisions to prevent unintended operations by preventing the generation of glitch noise at select signal transitions. The selector device includes a selector, controlled by a select signal, which selects either of two inputs (A or B), a noise mask generation circuit that delays input A, and a noise masking circuit that combines the output of the selector with the output of the noise mask generation circuit to generate an output signal free of glitch noise.